Method for comprehensive integration verification of mixed-signal circuits

ABSTRACT

Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.15/333,457, filed Oct. 25, 2016, which claims priority to, and thebenefit of, Indian provisional application number 5867/CHE/2015,entitled “METHOD FOR COMPREHENSIVE INTEGRATION VERIFICATION OFMIXED-SIGNAL CIRCUITS”, and filed in India on Oct. 30, 2015, theentirety of both are hereby incorporated by reference.

BACKGROUND

Mixed-signal circuits typically include both analog and digital circuitblocks, as well as ports for internal interconnections externalconnections. Modern circuit design often involves electronic designautomation (EDA) tools to simulate and verify circuit block operationand interconnections. However, most EDA tools do not provide for timeefficient verification of mixed-signal design integration. Inparticular, mixed-signal integration verification is a time consumingtask that often involves verifying thousands of connections andassociated control logic. Conventional simulation can be used to verifythe mixed-signal integration, but this involves excessive time forcomprehensive verification. The simulation time can be reduced byreducing the scope of verification, but this increases the chances ofincorrect designs being approved for production.

SUMMARY

Disclosed examples include methods for verifying mixed-signal circuitdesign, in which an executable specification file is generated includingintegration abstractions that represent an intended integration ofports, pins of digital and analog circuit blocks of a mixed-signaldesign, a formal properties file is automatically generated from theexecutable specification file, an analog circuit component of themixed-signal circuit design is modeled as a digital circuit component ina model file, at least one analog circuit block of the mixed-signalcircuit design is modeled as one or more ports in the model file, andcorrespondence of connections of the formal properties file and themodel file is verified with the mixed-signal circuit design to generatea coverage report file.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow diagram showing a method to verify integration of amixed-signal circuit design according to an embodiment of thedisclosure.

FIG. 2 is a schematic diagram of an example mixed-signal circuit design.

FIG. 3 is a flow diagram showing an example method of generating anexecutable specification file in the integration verification method ofFIG. 1 according to an embodiment of the disclosure.

FIG. 4 shows an example executable specification file corresponding tothe mixed-signal circuit design example of FIG. 2.

FIG. 5 is a flow diagram showing an example method of modeling analogcircuit components of a mixed-signal circuit design in the integrationverification method of FIG. 1 according to an embodiment of thedisclosure.

FIG. 6 shows an example formal properties file corresponding to themixed-signal circuit design example of FIG. 2.

FIGS. 7 and 8 show an example of modeling analog circuit components of amixed-signal circuit design in the integration verification method ofFIG. 1.

FIG. 9 is a schematic diagram showing black box modeling in the examplemixed-signal circuit design of FIG. 2 in the integration verificationmethod of FIG. 1.

FIG. 10 shows an example coverage report generated in the integrationverification method of FIG. 1.

DETAILED DESCRIPTION

In the drawings, like reference numerals refer to like elementsthroughout, and the various features are not necessarily drawn to scale.In the following discussion and in the claims, the terms “including”,“includes”, “having”, “has”, “with”, or variants thereof are intended tobe inclusive in a manner similar to the term “comprising”, and thusshould be interpreted to mean “including, but not limited to. . .”Disclosed examples include methods and techniques to verify integrationof mixed-signal circuit designs that include abstraction of the designintent and implementation details and generation of formal propertiesfor formal proof. The disclosed methods can be used in conjunction withcommercial EDA tools and systems for formal proof of a givenmixed-signal circuit design. In certain examples, a user is providedwith a netlist file defining a mixed-signal circuit design, and manuallyperforms certain steps using Verilog or other properties language toconstruct or generate an executable specification file in a row andcolumn format, such as a spreadsheet, that captures the mixed-signalintegration intent. Software is used to automatically generate a formalproperties file from the executable spec, and the user generates one ormore model files to model or represent analog components to enableapplication of formal proof methods. EDA tools can then be used to provethe properties according to a mixed-signal netlist, the formalproperties file and the model files, and the user can analyze coverageusing formal methods.

Referring initially to FIGS. 1-4, FIG. 1 shows a method 100 to verifyintegration of a mixed-signal circuit design according to an embodimentof the disclosure. The method 100 can be used in verifying integrationof any mixed-signal design, and is described hereinafter in associationwith the example mixed-signal circuit design 200 of FIG. 2. The method100 in one example begins with a netlist file or other design definitionrepresenting ports 202, one or more analog circuit blocks 206 and one ormore digital circuit blocks 204 or 208 of a mixed-signal circuit design200.

The example circuit design 200 of FIG. 2 includes externally accessibleinput and output ports or connections 202A and 202B, with correspondingport names or labels 203A and 203B shown in the drawing. The design 200also includes several circuit blocks 204, 206 and 208 (also referred toas sub-blocks) labeled as “IPs” in FIG. 2. A first digital circuit block204-1 is a control logic circuit block (labeled iIP1), and furtherdigital and analog (mixed-signal) circuit blocks 208A and 208B are gluelogic circuits operating on signals conveyed via port lines 202(collectively referred to as ports) and interconnections 210 of thedesign. As used herein, ports can be externally accessible and/or portsof internal circuit blocks 204, 206 and/or 208. The example design 200also includes analog circuit blocks 206, for example, programmable gainamplifier (PGA) circuits, other types of amplifier circuits, bandgap orother reference circuits, low dropout (LDO) regulator circuits,analog-to-digital converter (ADC) circuits, digital-to-analog converter(DAC) circuits, or so forth. The example 200 of FIG. 2 includes threeinstances of a first example analog circuit block, labeled as iIP2_A(206-2A), iIP2_B (206-2B) and iIP2_C (206-2C), as well as singleinstances of further analog circuit blocks I5 and iIP4 (206-4). Theexample 200 of FIG. 2 also includes an instance of analog circuit blocklabeled iIP3 (206-3) which is instantiated inside the analog circuit I5.I5 may have additional digital and analog circuits other than iIP3. FIG.2 shows example names 203 for the input and output ports 202 of thedesign 200. The input port names 203A include a first 16 line bus nameSEL_A<15:0>, a second 16 line bus name N_SEL<15:0>, a 32 line bus nameCONA<31:0>, and a power port is named VSS_TOP which includes digital andanalog power connections VSSD and VSSA. The input port names 203A alsoprovide for three 3-line buses corresponding to the three instances ofiIP2, respectively named IBIAS5UA<2:0>, IBIAS5UB<2:0> and IBIAS5UC<2:0>.In this example, a single output port name 203B is provided for anoutput line OUT2 of the output ports 202B.

The method 100 in FIG. 1 includes generating an executable specificationfile at 102, for example, based on an input netlist file (not shown) orother definition of the mixed-signal circuit design 200. In certainexamples, the design 200 includes definitions of a desired ports 202,interconnections 210, and circuit blocks 204, 206 and/or 208 as shown inFIG. 2. FIG. 4 shows an example executable specification file 400 thatincludes integration abstractions 402 that represent an intendedintegration of ports 202 and digital circuit blocks 208 of themixed-signal design 200. At 104, the method 100 includes automaticallygenerating a formal properties file (e.g., file 600 in FIG. 6 below)from the executable specification file 400 using a processor executedsoftware program. One or more analog circuit components are modeled at106 as a digital circuit component in a model file (not shown) forverification using an electronic design automation EDA tool, and atleast one analog circuit block 206 of the mixed-signal circuit design200 is modeled at 108 as one or more ports in the model file. The method100 further includes verifying correspondence of connections of theformal properties file 600 and the model file with the mixed-signalcircuit design 200 at 110 using a processor executing an electronicdesign automation EDA tool to generate a coverage report file 1000(e.g., FIG. 10 below). In one example, the correspondence is verified at110 by comparing the connections of the netlist file with the formalproperties file 600 and the model file(s). At 112, a user analyzes thecoverage report file 1000 to determine the amount of coverage of themixed-signal circuit design verification.

FIG. 3 shows details of an example method 300 to generate the executablespecification file 400 (FIG. 4) that can be used at 102 in the method100 of FIG. 1. In one example, a user manually generates the executablespecification file 400, which includes a plurality of integrationabstractions 402 that represent an intended integration of ports 202 anddigital circuit blocks 208 of the mixed-signal design 200. In oneexample, the mixed-signal design 200 is represented as a netlist file,and the executable specification file 400 is generated at 102 accordingto the netlist file. In one implementation, the user can employ one ormore abstractions referred to herein as COND, ASSIGN, OPEN, IF/ELSE andPRINT abstractions to capture the integration intent of the mixed-signaldesign 200 in a column and row format (e.g., by creating a spreadsheetfile with Verilog or other language that can be processed by a formalEDA tool.

The example of FIG. 4 provides a specific format of an executablespecification file 400 for capturing the integration intent that is easyto fill and review, with the capability to capture direct connections,complex control logic (digital and analog), switches, bus splits anddirect printing. The process 300 in FIG. 3 is described below inconjunctions with the column and row format of FIG. 4. Other formats canbe used in other implementations, for example, extended markup language(XML). In the example of FIG. 4, the executable specification file 400includes C1-C8, and seven example rows R0-R6 are illustrated in thedrawing. The first column C1 is labeled “TOPBLOCK” in FIG. 4 andincludes names 404 of externally accessible ports 202 of the design 200.In the illustrated example, row R1 includes an entry “OUT2” designatingthe name 203B of the output port 202B in FIG. 2, and row R5 includes anentry in the first column C1 for the digital and analog supply portVSS_TOP. A second column C2 includes entries 406-1 and abstractionsusing corresponding constructs 410-414 corresponding to the controllogic circuit block 204-1 and for open (e.g., unconnected) ports in themixed-signal circuit design 200. The third column C3 in this exampleincludes comments provided by the user. The remaining columns C4, C5,C6, C7 and C8 are used for representing abstractions of the remainingcircuit blocks 206. Columns 4-6 include labels 406-2A (IP2:iIP2_(A)),406-2B (IP2:iIP2_(B)) and 406-2C_(C)) for the three instances 206-2A,206-2B and 206-2C of iIP2 in FIG. 2. The seventh column C7 in theexecutable specification file 400 includes a label 406-3 (IP3:iIP3)corresponding to the circuit block 206-3, and the final column C8includes a label 406-4 (IP4:iIP4) corresponding to the circuit block206-4 in the mixed-signal circuit design 200. The rows R2-R6 defineinterconnections between the circuit blocks of the design 200, and eachmatch between entries in a given row indicates a connection within thedesign 200. The row R0 captures the root hierarchical path of each ofthe analog blocks in the design. The common root path is given in columnC2 (in the example shown the common root path is TOP 420). If the modulehas a root path that is different than one given in column C2, then itis given in the modules respective column. In the example module IP3 sinstance iIP3's root path is TOP.I5 which is different than TOP andhence it is given in its column 422.

The user can introduce or add one or more abstractions or constructs tothe executable specification file 400 according to a particularmixed-signal circuit design integration intent at 102 in FIG. 1. FIG. 3shows a detailed flow diagram of a process 300 by which the usercaptures the integration intent in the executable specification file400. At 302 in FIG. 3, the user adds a first construct $A (e.g., 411 inFIG. 4) to the executable specification file 400 to represent internaldirect connections of the mixed-signal design 200. The $A( ) construct411 is used to capture an ASSIGN abstraction in the executablespecification file 400 for internal direct connections between theanalog circuit blocks. Direct connections with the top level ports 202are captured in this example by the user including the port name in adifferent position without having to use the $A construct 411. The namegiven in the $A( ) construct is a new name for the internal assignment.In the example of FIG. 4, the abstraction $A(IBIAS5U\1<2:0.) In row R2corresponds with the entries IBIAS5UA<2:0>, IBIAS5UB<2:0> andIBIAS5UC<2:0> in columns C4-C6 of the same row, and a “\” construct 410in this case indicates that the three lines of IBIAS5UA<2:0> areinternally connected to the first instance of iIP2_A, the three lines ofIBIAS5UB<2:0> are internally connected to the first instance of iIP2_B,and the three lines of IBIAS5UC<2:0> are internally connected to thefirst instance of iIP2_C. This example further illustrates the construct“< >” described further below.

At 304 in FIG. 3, the user adds a second construct 412, $COND and atleast one logic expression to the executable specification file 400 torepresent a control logic circuit block 204 of the mixed-signal design200. The $COND( ) construct 412 is used to capture complex control andmixed-signal logic between either top level ports 202 and/or between theanalog circuit blocks 204, 206 themselves. In certain examples, thecontrol logic abstraction 406-1 in the executable specification file 400can include any expression used in Verilog (or other languages readableby EDA tools). In the example of FIG. 4, the user adds the construct 412in row R3 with the expression for connection of the 16 line busesSEL_A<15:0> and N_SEL<15:0> to the first instance of iIP2_A circuitblock 206-2A via the control logic circuit block 204-1 that is capturedby the abstraction 406-1 in the executable specification file 400.

At 306 in FIG. 3, the user adds a third construct 413 ($OPEN) to theexecutable specification file 400 to represent unconnected externalports of the mixed-signal circuit design 200. For example, the user addsthe construct 413 in row R6 of the specification file 400 of FIG. 4 toindicate that external gain (EXT_GAIN) ports or connections of the threeinstances of the analog circuit block iIP2_A (206-2A), iIP2_B (206-2B)and iIP2_C (206-2C) are not intended to be connected anywhere within theintegrated mixed-signal circuit design 200.

At 308 in FIG. 3, the user adds a fourth construct 414 ($IF) to theexecutable specification file 400 to represent a switched connection ofthe mixed-signal design 200. The $IF( ) construct allows the user tocapture the IF/ELSE abstraction for switched connections between eithertop level ports and/or between the circuit blocks themselves. In oneexample, the user adds the $IF ( ) construct in situations where thereis no “ELSE” portion. In the illustrated example, the user adds theconstruct $IF( ) in the second column C2 of row R4 including anexpression CONA<21>? (4′b0 ? CONA<20:17>) representing logic of theabstracted control logic circuit block 204-1 in FIG. 2 for a connectionof CONFIG<7:4> to the circuit block 206-2A shown in row R4 of the columnC4.

At 310, the user adds a fifth construct $PRINT to the executablespecification file 400 (not shown in the example of FIG. 4). The $PRINTconstruct can be used to represent elements of the mixed-signal design200 that cannot be represented by any of the first, second, third orfourth constructs or abstractions ASSIGN, OPEN, COND or IF/ELSEabstractions. The content in PRINT abstraction in one example isdirectly dumped in to the formal properties file.

At 312, the user adds a sixth construct 416 (“/”) to the executablespecification file 400 to represent multiple connections to a singleport 202, or multiple connections to a single circuit block 204, 206,208 of the mixed-signal circuit design 200. The “/” construct 416 in theport or connection name of the design 200 captures multiple ports orconnections that are connected to the same port or logic. For example,the use of the construct 416 in the entries VSS/VSS in columns C4-C8 inrow R5 of FIG. 4 indicates two connections: (1) VSS_TOP to an analogsupply VSSA and (2) VSS_TOP to a digital supply VSSD. At 314, the useradds a seventh construct 417 (“< >”) to the executable specificationfile 400 to represent a normal bus of the mixed-signal design 200. Theuser may also add an eighth construct “{ }” (not shown in the example ofFIG. 4) at 316 in FIG. 3 to represent a complex bus of the mixed-signaldesign 200. For example, the user in FIG. 4 adds the “< >” constructs416 in row R2 for the bias current bus signal connections IBIAS5U<2:0>.In certain examples, the user can construct a complex bus using the “{}” construct, where the contents of the complex bus can be any port orassigned signal such as {IBIAS5UA<2>, INSEL<5>, CONFIG<31:15>}. Complexbuses are given in the logic section (column C2 in executable file 400).At 318, the user adds a ninth construct “//” to the executablespecification file 400 to comment connections in the entire row of theexecutable specification by adding the same first column C1 for thecorresponding row. If details are added for a particular connection theycan be added in the comment section (column C3 in executable file 400)without having to comment the entire connection.

Regular expression is used in certain examples to connect similarlynamed signals to different instances of the same module. For example,the module IP2 has three instances in FIG. 4, each connected to bitIBIAS5U<2:0>. For the instance iIP2_A of this module user, the designerhas connected this to port IBIAS5UA<2:0>, for instance iIP2_B toIBIAS5UB<2:0>, and for instance iIP2_C to IBIAS5UC<2:0>. This connectionis presented as IBIAS5U\1<2:0> in the abstraction 406-1 of FIG. 4, where“\1” is used to indicate the instance name replacement. The replacementfor the name comes from the value given in the braces after the analogIP module name e.g., “IP2:iIP2_(A)” and “IP2:iIP2_(B)”. If complexnaming is used for the instance with multiple sub-sections they are alsohandled by using name replacement positions up to “\n” where “n” is thenumber of sub-sections. For example, if instance name is IA_1 and IB_2and the ports are named as IBIAS5UA1 and IBIAS5UB2 then the ports arecaptured in the executable specification as IBIAS5U\1\2<2:0> andinstance name is captured as “IP2:I(A)_(1)” and “IP2:I(B)_(2)”.

Referring now to FIGS. 1, 5 and 6, formal assertions are automaticallygenerated at 104 in FIG. 1 from the executable specification file 400 toconstruct a formal properties file 600 shown in FIG. 6. FIG. 5 shows anexample method 500 for generating the formal properties file 600 whichcan be employed at 104 in one implementation of the integrationverification method 100 of FIG. 1. The executable specification file 400in one example is parsed and analyzed at 104 using processor-executedsoftware (not shown) for any errors by comparing with the mixed-signalmodules Verilog netlist. Formal properties are then generated based onthe integration type (e.g., conditional, if/else and assign). At 502 inFIG. 5, the processor processes the first two lines of the executablespecification file 400 to obtain the following details: (a) Position ofthe port details, logic details, comment and analog circuit block (IP)details, (b) all Analog IP names, and (c) all Analog IP instance namesand their full hierarchical path. At 504, the processor processes any“PRINT” abstraction captured using the $PRINT( ) construct, and storesthe contents of the PRINT abstraction.

At 506, the processor processes any “IF/ELSE” abstraction captured usingthe $IF( ) construct 414 and determines the control condition and theassignment, determines connections for condition pass and fail cases.Once the assignment is determined, the processor ascertains the buswidth of the source and the destination, compares the bus widths to makesure they are same, and if not issues a report error. The processorstores the connections determined for the “IF/ELSE” abstraction, andrepeats for any other instances.

At 508, the processor processes any “ASSIGN” abstraction capturingdirect connections from port (404 in illustrated example) to individualanalog circuit block ports or pins by giving the port name and modulepins. The processor expands the instance substitution in the name (“\n”construct), expands multiple connections in the same instance (“/”construct), and expands buses of source and destination (“< >”construct). The processor then checks if the bus widths are the same,and reports an error if not. The processor stores the connectionsdetermined for the “ASSIGN” abstraction between the top level port andcircuit block port (e.g., module pin), and repeats for any otherinstances.

At 510, the processor processes any “COND” abstraction that was capturedin the executable specification file 400 using the $COND( ) construct412 capturing internal connections between analog module pins andcomplex buses constructed from a top level port 202 to analog modulepins captured using $COND( ) construct. The processor expands theinstance substitution in the name (“\n” construct) and also expandsmultiple connections in the same instance (“/” construct). The processorfurther checks whether the bus width of the instance net is ONE (sincecontrol logic can be connected to a single net and not a bus), obtainsthe value of control in $COND( ) construct, stores the connections andcontrols determined for the “COND” abstraction, and repeats for anyother instances.

At 512, the processor processes any “ASSIGN” abstraction captured usingthe $A( ) construct 411 in the specification file 400 for directconnections from a port to individual analog module pins. The processorexpands the instance substitution in the name (“\n” construct), expandsmultiple connections in the same instance (“/” construct), expands busesof source and destination (“< >” construct), checks if the bus widthsare the same, stores the connections determined for “ASSIGN” abstractioncaptured via the $A( ) construct 411, stores the net name and its MSB(Most Significant Bit) given in $A( ) construct, and repeats for otherinstances.

At 514, the processor processes any “OPEN” abstraction captured usingthe $OPEN( ) construct in the executable specification file 400 for openconnection in the module pins. The processor expands the instancesubstitution in the name (“\n” construct), expands multiple connectionsin the same instance (“/” construct), stores the connections determinedfor “OPEN” abstraction captured via $OPEN( ) construct, and repeats forother instances.

At 516, the processor processes any “ASSIGN” abstraction capturingdirect connections “assigned net” and individual analog module pinswhich were captured by giving the “assigned net” name and module pins(424). The processor expands the instance substitution in the name (“\n”construct) and expands multiple connections in the same instance (“/”construct). If a complex bus is abstracted, the processor stores theconnections, and if a simple bus is abstracted (“< >” construct), theprocessor expands the source and destination buses. The processor checksif the bus widths are the same, and if not, reports and error. Theprocessor then stores the connections and repeats for other instances.

At 518, the processor performs final processing to generate the formalproperties file 600, such as the example shown in FIG. 6. The processorchecks all module pins accounted for in the executable specification,processes respective analog modules from a corresponding Verilog file(e.g., netlist file) to get module port info, consolidates all pins formodule in the executable specification file 400, compares pins in theexecutable specification file 400 and the corresponding Verilog file,and reports any pin mismatches. The processor generates the propertiesfile 600 at 518 using the data stored in earlier steps in FIG. 5.

Referring now to FIGS. 1, 7 and 8, the user in one example manuallymodels 106 one or more analog circuit components of the mixed-signalcircuit design 200 at 106 in FIG. 1 as digital circuit components. FIG.8 shows example user modelings 800 by which the user models on analogcircuit component 810 as a digital circuit component 812. In oneexample, the user models resistor components 810A as short circuitdigital components 812A via a modeling 802. A modeling 804 in FIG. 8shows modeling of an analog capacitor 810B as an open circuit 812B.Modelings 806 and 808 provide for modeling transistor circuits 810C or810D as tri-state buffer circuits 812C or 812D. The inventor hasappreciated that components of mixed-signal integration logic ofteninclude (a) digital gates, (b) resistors 810A, (c) capacitors 810B, (d)transistors 810C and (e) pass gate switches 810D. In certain embodimentsof the present disclosure, the user respectively models these as (a) RTL(Register Transfer Level) model, (b) wire, (c) open circuits and (d, e)tristate buffers with appropriate control logic in a model file 700. Incertain examples, the model file 700 includes one or more model filesections or components implemented in Verilog language, such as 702(resistor model), 704 (capacitor model), NMOS transistor model 706A (RTLtransistor model), PMOS transistor model (706B), and a model component708 (pass gate switch model). In this manner, the modeling process at106 includes manually replacing a resistor 810A of the mixed-signalcircuit design 200 with a short circuit 812A in the model file 700,and/or replacing a capacitor 810B of the mixed-signal circuit design 200with an open circuit 812B in the model file 700, and/or replacing atransistor circuit 810C, 810D of the mixed-signal circuit design 200with a tristate buffer circuit 812C, 812D in the model file 700. Asshown in FIG. 8, the processing 106 may include replacing a transistor810C of the mixed-signal circuit design 200 with a tristate buffercircuit 812C in the model file, and/or or replacing a pass gate circuit810D with a logic controlled tristate buffer circuit 812D in the modelfile. With these abstracted models in a model file 700, the netlist canhave combinatorial loops formed due to resistors/transistors beingtransformed as combinational logic. These loops can be broken byupdating the netlist or by use of an EDA tool to break the same.

Referring now to FIGS. 1 and 9, examples of the method 100 furtherinclude modeling one or more analog circuit blocks 206 of the design 200at 108 as one or more ports in the model file. This effectively allowsthe subsequent formal verification to treat the modeled circuit blocks206 as “black boxes” in order to focus the automated formal verificationprocessing (e.g., using EDA tools) on integration verification. Theinventor has appreciated that larger analog components are generally nota part of the integration logic and hence we can be modeled as blackboxes. The black box modeling at 108 also helps in (a) reducing theruntime analysis, (b) focusing on coverage of the critical sections and(c) preventing false errors being identified in the later steps (e.g.,reduces false negatives). In the example of FIG. 9, the user manuallydesignates certain analog circuit blocks 206-2A, 206-2B, 206-2C, 206-3and 206-4 in FIG. 9 to be modeled as ports (e.g., black boxed) forformal verification of the mixed-signal circuit design 200.

Referring also to FIG. 10, formal methods are then used at 110 in FIG. 1to prove the generated properties represented by the initial netlist orother file defining the initial integration intent, the formalproperties file 600 (FIG. 6) and any model files 700 created at 106and/or 108. In certain examples, this includes using a processorexecuting an EDA tool (not shown) to generate a coverage report file1000 shown in FIG. 10. If the properties fail, they are then debuggedand appropriate actions are taken. At 112, the tool generates thecoverage report file 1000 for analysis by the user. The generatedcoverage file 1000 indicates coverage for the pins of the analog modules(circuit block ports) and ports 202 at the top level and logic 204 and208 in between. The coverage report 1000 provides integration andconnection coverage, and the user analyzes the coverage data at 112 toensure comprehensive verification of the mixed-signal integration.

The disclosed methods 100, 300 and 500 facilitate mixed-signal analogand digital circuit design verification that focuses the verificationprocessing on the integration intent for a particular design 200. This,in turn, facilitates significant reduction in verification time usingEDA tools compared with conventional simulation techniques. For example,a complex mixed-signal I/O circuit design having 26 analog circuitblocks (analog IPs), 2700 IO Ports, 13,000 internal connections and 120complex control logic conditions (with at least 10 literals in eachcondition) for a design having approximately 15% analog circuitry and85% digital circuitry has an estimated comprehensive verification usingtraditional simulation over approximately 30 days. Such a design wasverified using the above-described techniques, including generation of1099 properties in a formal properties file 600 for all connections andconditional logic, black box modeling of 26 instances of eight analogcircuit blocks (analog IPs), with a runtime of approximately 10 minutes,representing a 5000× improvement for the same quality over simulation.In one example, iterations for new netlist can take approximately half aday depending on design complexity, and the verification identifiedactual design bugs related to control bus expansion. 60 additionalfunctional simulations were used to verify dependency and functionaloperation, for example resistor value programmability, analog programmetrics, sequencing the, etc. The disclosed techniques can beadvantageously employed to facilitate comprehensive integrationverification and coverage analysis of mixed-signal integration.

The above examples are merely illustrative of several possibleembodiments of various aspects of the present disclosure, whereinequivalent alterations and/or modifications will occur to others skilledin the art upon reading and understanding this specification and theannexed drawings. Modifications are possible in the describedembodiments, and other embodiments are possible, within the scope of theclaims.

The following is claimed:
 1. A method to verify integration of amixed-signal circuit design, the method comprising: generating anexecutable specification file in a column and row format, the executablespecification file including a plurality of integration abstractionsthat represent an intended integration of ports, analog circuit blocks,and digital circuit blocks of the mixed-signal design, wherein a firstcolumn represents ports, wherein a second column represents controllogic as integration abstractions, and wherein one or more columns eachrepresent one of the analog or digital circuit blocks and in which anentry indicates a connection within the mixed-signal design; processingthe integration abstractions in the executable specification file usinga processor executing a software program to generate a formal propertiesfile; modeling an analog circuit component of the mixed-signal circuitdesign as a digital circuit component in a model file; modeling at leastone analog circuit block of the mixed-signal circuit design as one ormore ports in the model file; and verifying correspondence ofconnections and integration of the formal properties file and the modelfile with the mixed-signal circuit design using a processor executing anelectronic design automation (EDA) tool to generate a coverage reportfile wherein at least one of the integration abstractions in theexecutable specification file is of one of a plurality of constructtypes comprising: a first construct for representing assignment ofinternal direct connections of the mixed-signal design; a secondconstruct indicating at least one logic expression for representingconditional logic expressions in the control logic of the mixed-signaldesign; a third construct for representing unconnected external ports ofthe mixed-signal circuit design; or a fourth construct for representingswitched internal connections of the mixed-signal design.
 2. The methodof claim 1, further comprising: analyzing the coverage report file todetermine an amount of coverage of the mixed-signal circuit designverification.
 3. The method of claim 1, wherein the mixed-signal designis represented as a netlist file, and wherein the executablespecification file is generated according to the netlist file.
 4. Themethod of claim 3, wherein verifying correspondence of the connectionsand integration of the formal properties file with the mixed-signalcircuit design comprises comparing the connections of the netlist filewith the formal properties file and the model file.
 5. The method ofclaim 1, wherein at least one of the integration abstractions in theexecutable specification file is of a fifth construct for representingelements of the mixed-signal design that cannot be represented by any ofthe first, second, third or fourth constructs.
 6. The method of claim 1,wherein one or more of the integration abstractions includes at leastone of a plurality of constructs comprising: a construct representingmultiple connections to a single port or a single circuit block of themixed-signal circuit design; a construct representing a normal bus ofthe mixed-signal design; an construct representing a complex bus of themixed-signal design; and a construct representing a whole connection ofthe mixed-signal design.
 7. The method of claim 1, wherein modeling theanalog circuit component of the mixed-signal circuit design as a digitalcircuit component includes at least one of: replacing a resistor of themixed-signal circuit design with a short circuit in the model file;replacing a capacitor of the mixed-signal circuit design with an opencircuit in the model file; or replacing a transistor circuit of themixed-signal circuit design with a tristate buffer circuit in the modelfile.
 8. The method of claim 7, wherein replacing the transistor circuitof the mixed-signal circuit design with a tristate buffer circuitfurther includes at least one of: replacing a transistor of themixed-signal circuit design with a tristate buffer circuit in the modelfile); or replacing a pass gate circuit of the mixed-signal circuitdesign with a logic controlled tristate buffer circuit in the modelfile.
 9. A method of verifying integration of a mixed-signal circuitdesign, the method comprising: generating an executable specificationfile in an extended markup language (XML) format, the executablespecification file including a plurality of integration abstractionsthat represent an intended integration of ports and digital and analogcircuit blocks of the mixed-signal design; processing the integrationabstractions in the executable specification file, using a processorexecuting a software program, to generate a formal properties filerepresenting the intended integration of ports and digital and analogcircuit blocks of the mixed-signal design; modeling an analog circuitcomponent of the mixed-signal circuit design as a digital circuitcomponent in a model file for verification using an electronic designautomation (EDA) tool wherein at least one of the integrationabstractions in the executable specification file is of one of aplurality of construct types comprising: a first construct forrepresenting assignment of internal direct connections of themixed-signal design; a second construct indicating at least one logicexpression for representing conditional logic expressions in the controllogic of the mixed-signal design; a third construct for representingunconnected external ports of the mixed-signal circuit design; or afourth construct for representing switched internal connections of themixed-signal design.
 10. The method of claim 9, wherein modeling theanalog circuit component of the mixed-signal circuit design as a digitalcircuit component includes at least one of: replacing a resistor of themixed-signal circuit design with a short circuit in the model file;replacing a capacitor of the mixed-signal circuit design with an opencircuit in the model file; or replacing a transistor circuit of themixed-signal circuit design with a tristate buffer circuit in the modelfile.
 11. The method of claim 9, wherein replacing the transistorcircuit of the mixed-signal circuit design with a tristate buffercircuit further includes at least one of: replacing a transistor of themixed-signal circuit design with a tristate buffer circuit in the modelfile; or replacing a pass gate circuit of the mixed-signal circuitdesign with a logic controlled tristate buffer circuit in the modelfile.